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LTC2159 1 2159f typical a pplica t ion descrip t ion 16-bit, 20msps low power adc the ltc ? 2159 is a sampling 16-bit a/d converter designed for digitizing high frequency, wide dynamic range signals. it is perfect for demanding communications applications with ac performance that includes 77db snr and 90db spurious free dynamic range (sfdr). ultralow jitter of 0.07ps rms allows undersampling of if frequencies with excellent noise performance. dc specs include 2lsb inl (typ), 0.5lsb dnl (typ) and no missing codes over temperature. the transition noise is 3.2lsb rms . the digital outputs can be either full rate cmos, double data rate cmos, or double data rate lvds. a separate output power supply allows the cmos output swing to range from 1.2v to 1.8v. the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl, or cmos inputs. an optional clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. integral non-linearity (inl) fea t ures a pplica t ions n 77db snr n 90db sfdr n low power: 43mw n single 1.8v supply n cmos, ddr cmos, or ddr lvds outputs n selectable input ranges: 1v p-p to 2v p-p n 550mhz full power bandwidth s/h n optional data output randomizer n optional clock duty cycle stabilizer n shutdown and nap modes n serial spi port for configuration n 48-lead (7mm 7mm) qfn package n communications n cellular base stations n software defined radios n portable medical imaging n multichannel data acquisition n nondestructive testing s/h output drivers 16-bit adc core clock control d15 ? ? ? d0 20mhz clock analog input 2159 ta01a cmos ddr cmos or ddr lvds outputs 1.8v v dd 1.8v ov dd gnd ognd output code 0 ?4.0 ?3.0 ?2.0 ?1.0 inl error (lsb) 0 1.0 4.0 3.0 2.0 16384 32768 49152 65536 2159 ta01b
LTC2159 2 2159f a bsolu t e maxi m u m r a t ings supply voltages (v dd , o vdd ) ....................... C0 .3v to 2v analog input voltage (a in + , a in C , par/ ser , sense) (note 3) ................................... C 0.3v to (v dd + 0.2v) digital input voltage (enc + , enc C , cs , sdi, sck) (note 4) ................................................ C 0.3v to 3.9v sdo (note 4) ............................................. C 0.3v to 3.9v (notes 1, 2) full rate cmos output mode double data rate cmos output mode top view 49 gnd uk package 48-lead (7mm 7mm) plastic qfn v cm 1 a in + 2 a in ? 3 gnd 4 refh 5 refl 6 refh 7 refl 8 par/ ser 9 gnd 10 gnd 11 v dd 12 36 d11 35 d10 34 d9 33 d8 32 ov dd 31 ognd 30 clkout + 29 clkout ? 28 d7 27 d6 26 d5 25 d4 48 v dd 47 v dd 46 sense 45 v ref 44 sdo 43 gnd 42 of 41 dnc 40 d15 39 d14 38 d13 37 d12 v dd 13 gnd 14 enc + 15 enc ? 16 cs 17 sck 18 sdi 19 gnd 20 d0 21 d1 22 d2 23 d3 24 t jmax = 150c, ja = 29c/w exposed pad (pin 49) is gnd, must be soldered to pcb top view 49 gnd uk package 48-lead (7mm 7mm) plastic qfn v cm 1 a in + 2 a in ? 3 gnd 4 refh 5 refl 6 refh 7 refl 8 par/ ser 9 gnd 10 gnd 11 v dd 12 36 d10_11 35 dnc 34 d8_9 33 dnc 32 ov dd 31 ognd 30 clkout + 29 clkout ? 28 d6_7 27 dnc 26 d4_5 25 dnc 48 v dd 47 v dd 46 sense 45 v ref 44 sdo 43 gnd 42 of 41 dnc 40 d14_15 39 dnc 38 d12_13 37 dnc v dd 13 gnd 14 enc + 15 enc ? 16 cs 17 sck 18 sdi 19 gnd 20 dnc 21 d0_1 22 dnc 23 d2_3 24 t jmax = 150c, ja = 29c/w exposed pad (pin 49) is gnd, must be soldered to pcb p in c on f igura t ion digital output voltage ................ C 0.3v to (ov dd + 0.3v) operating temperature range LTC2159c ................................................ 0 c to 70c LTC2159i ............................................. C 40c to 85c storage temperature range .................. C 65c to 150c
LTC2159 3 2159f o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range LTC2159cuk#pbf LTC2159cuk#trpbf LTC2159uk 48-lead (7mm 7mm) plastic qfn 0c to 70c LTC2159iuk#pbf LTC2159iuk#trpbf LTC2159uk 48-lead (7mm 7mm) plastic qfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ pin con f igura t ion double data rate lvds output mode top view 49 gnd uk package 48-lead (7mm 7mm) plastic qfn v cm 1 a in + 2 a in ? 3 gnd 4 refh 5 refl 6 refh 7 refl 8 par/ ser 9 gnd 10 gnd 11 v dd 12 36 d10_11 + 35 d10_11 ? 34 d8_9 + 33 d8_9 ? 32 ov dd 31 ognd 30 clkout + 29 clkout ? 28 d6_7 + 27 d6_7? 26 d4_5 + 25 d4_5? 48 v dd 47 v dd 46 sense 45 v ref 44 sdo 43 gnd 42 of + 41 of ? 40 d14_15 + 39 d14_15 ? 38 d12_13 + 37 d12_13 ? v dd 13 gnd 14 enc + 15 enc ? 16 cs 17 sck 18 sdi 19 gnd 20 d0_1 ? 21 d0_1 + 22 d2_3 ? 23 d2_3 + 24 t jmax = 150c, ja = 29c/w exposed pad (pin 49) is gnd, must be soldered to pcb
LTC2159 4 2159f c onver t er c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. parameter conditions min typ max units resolution (no missing codes) l 16 bits integral linearity error differential analog input (note 6) l C6 2 6 lsb differential linearity error differential analog input l C0.9 0.5 0.9 lsb offset error (note 7) l C7 1.5 7 mv gain error internal reference external reference l C1.8 1.5 C0.5 0.8 %fs %fs offset drift 10 v/c full-scale drift internal reference external reference 30 10 ppm/c ppm/c transition noise external reference 3.2 lsb rms a nalog i npu t the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.7v < v dd < 1.9v l 1 to 2 v p-p v in(cm) analog input common mode (a in + + a in C )/2 differential analog input (note 8) l 0.7 v cm 1.25 v v sense external voltage reference applied to sense external reference mode l 0.625 1.250 1.300 v i incm analog input common mode current per pin, 20msps 32 a i in1 analog input leakage current (no encode) 0 < a in + , a in C < v dd l C1 1 a i in2 par/ ser input leakage current 0 < par/ ser < v dd l C3 3 a i in3 sense input leakage current 0.625 < sense < 1.3v l C3 3 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter single-ended encode differential encode 0.07 0.09 ps rms cmrr analog input common mode rejection ratio 80 db bw-3b full power bandwidth figure 6 test circuit 550 mhz dyna m ic a ccuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions min typ max units snr signal-to-noise ratio 5mhz input 30mhz input 70mhz input 140mhz input l 75.5 77.1 77.0 76.9 76.4 dbfs dbfs dbfs dbfs sfdr spurious free dynamic range 2nd harmonic 5mhz input 30mhz input 70mhz input 140mhz input l 84 90 90 89 84 dbfs dbfs dbfs dbfs sfdr spurious free dynamic range 3rd harmonic 5mhz input 30mhz input 70mhz input 140mhz input l 84 90 90 89 84 dbfs dbfs dbfs dbfs
LTC2159 5 2159f d yna m ic accuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions min typ max units sfdr spurious free dynamic range 4th harmonic or higher 5mhz input 30mhz input 70mhz input 140mhz input l 89 95 95 95 95 dbfs dbfs dbfs dbfs s/(n+d) signal-to-noise plus distortion ratio 5mhz input 30mhz input 70mhz input 140mhz input l 74.9 76.9 76.8 76.5 76.4 dbfs dbfs dbfs dbfs parameter conditions min typ max units v cm output voltage i out = 0 0.5?v dd C 25mv 0.5?v dd 0.5?v dd + 25mv v v cm output temperature drift 25 ppm/c v cm output resistance C600a < i out < 1ma 4 v ref output voltage i out = 0 1.225 1.250 1.275 v v ref output temperature drift 25 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v i n t ernal r e f erence c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) digi t al i npu t s an d o u t pu t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) differential encode mode (enc C not tied to gnd) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.6 v v v in input voltage range enc + , enc C to gnd l 0.2 3.6 v r in input resistance (see figure 10) 10 k c in input capacitance (note 8) 3.5 pf single-ended encode mode (enc C tied to gnd) v ih high level input voltage v dd = 1.8v l 1.2 v v il low level input voltage v dd = 1.8v l 0.6 v v in input voltage range enc + to gnd l 0 3.6 v r in input resistance (see figure 11) 30 k c in input capacitance (note 8) 3.5 pf digital inputs ( cs, sdi, sck in serial or parallel programming mode. sdo in parallel programming mode) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance (note 8) 3 pf
LTC2159 6 2159f d igi t al inpu t s an d ou t pu t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units sdo output (serial programming mode. open drain output. requires 2k? pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance (note 8) 3 pf digital data outputs (cmos modes: full data rate and double data rate) ov dd = 1.8v v oh high level output voltage i o = C500a l 1.750 1.790 v v ol low level output voltage i o = 500a l 0.010 0.050 v ov dd = 1.5v v oh high level output voltage i o = C500a 1.488 v v ol low level output voltage i o = 500a 0.010 v ov dd = 1.2v v oh high level output voltage i o = C500a 1.185 v v ol low level output voltage i o = 500a 0.010 v digital data outputs (lvds mode) v od differential output voltage 100? differential load, 3.5ma mode 100? differential load, 1.75ma mode l 247 350 175 454 mv mv v os common mode output voltage 100? differential load, 3.5ma mode 100? differential load, 1.75ma mode l 1.125 1.250 1.250 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100 symbol parameter conditions min typ max units cmos output modes: full data rate and double data rate v dd analog supply voltage (note 10) l 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.1 1.8 1.9 v i vdd analog supply current dc input sine wave input l 24 24.4 28.5 ma ma i ovdd digital supply current sine wave input, ov dd =1.2v 0.8 ma p diss power dissipation dc input sine wave input, ov dd =1.2v l 43 45 51.5 mw mw lvds output mode v dd analog supply voltage (note 10) l 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.7 1.8 1.9 v i vdd analog supply current sine wave input, 1.75ma mode sine wave input, 3.5ma mode l 25.8 26.7 31 ma ma i ovdd digital supply current (ov dd = 1.8v) sine wave input, 1.75ma mode sine wave input, 3.5ma mode l 21.1 40.9 46 ma ma p diss power dissipation sine wave input, 1.75ma mode sine wave input, 3.5ma mode l 84 122 139 mw mw p ower r equire m en t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9)
LTC2159 7 2159f symbol parameter conditions min typ max units all output modes p sleep sleep mode power 1 mw p nap nap mode power 10 mw p diffclk power increase with differential encode mode enabled (no increase for nap or sleep modes) 20 mw power require m en t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) ti m ing c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units f s sampling frequency (note 10) l 1 20 mhz t l enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 20 2 25 25 500 500 ns ns t h enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 20 2 25 25 500 500 ns ns t ap sample-and-hold acquisition delay time 0 ns digital data outputs (cmos modes: full data rate and double data rate) t d enc to data delay c l = 5pf (note 8) l 1.1 1.7 3.1 ns t c enc to clkout delay c l = 5pf (note 8) l 1 1.4 2.6 ns t skew data to clkout skew t d C t c (note 8) l 0 0.3 0.6 ns pipeline latency full data rate mode double data rate mode 6 6.5 cycles cycles digital data outputs (lvds mode) t d enc to data delay c l = 5pf (note 8) l 1.1 1.8 3.2 ns t c enc to clkout delay c l = 5pf (note 8) l 1 1.5 2.7 ns t skew data to clkout skew t d C t c (note 8) l 0 0.3 0.6 ns pipeline latency 6.5 cycles spi port timing (note 8) t sck sck period write mode readback mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck setup time l 5 ns t h sck to cs setup time l 5 ns t ds sdi setup time l 5 ns t dh sdi hold time l 5 ns t do sck falling to sdo valid readback mode, c sdo = 20pf, r pullup = 2k l 125 ns
LTC2159 8 2159f e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 20mhz, lvds outputs, differential enc + /enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: v dd = 1.8v, f sample = 20mhz, cmos outputs, enc + = single- ended 1.8v square wave, enc C = 0v, input range = 2v p-p with differential drive, 5pf load on each digital output unless otherwise noted. note 10: recommended operating conditions. ti m ing diagra m s full-rate cmos output mode timing all outputs are single-ended and have cmos levels t h t d t c t l n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 t ap n + 1 n + 2 n + 4 n + 3 n analog input enc ? enc + clkout + clkout ? d0?d15, of 2159 td01
LTC2159 9 2159f double data rate cmos output mode timing all outputs are single-ended and have cmos levels t i m ing d iagra m s double data rate lvds output mode timing all outputs are differential and have lvds levels t h t d ? ? ? t d t c t c t l of n-6 of n-5 of n-4 of n-3 d0 n-6 d1 n-6 d0 n-5 d1 n-5 d0 n-4 d1 n-4 d0 n-3 d1 n-3 d14 n-6 d15 n-6 d14 n-5 d15 n-5 d14 n-4 d15 n-4 d14 n-3 d15 n-3 t ap n + 1 n + 2 n + 4 n + 3 n analog input enc ? enc + d0_1 d14_15 clkout + clkout ? of 2159 td02 t h t d t d t c t c t l of n-6 of n-5 of n-4 of n-3 d0 n-6 d1 n-6 d0 n-5 d1 n-5 d0 n-4 d1 n-4 d0 n-3 d1 n-3 d14 n-6 d15 n-6 d14 n-5 d15 n-5 d14 n-4 d15 n-4 d14 n-3 d15 n-3 t ap n + 1 n + 2 n + 4 n + 3 n analog input enc ? enc + d0_1 + d0_1 ? d14_15 + d14_15 ? clkout + clkout ? of + of ? 2159 td03 ? ? ?
LTC2159 10 2159f t i m ing d iagra m s a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 2159 td04 cs sck sdi r/w sdo high impedance integral non-linearity (inl) differential non-linearity (dnl) shorted input histogram typical p er f or m ance c harac t eris t ics output code 0 ?4.0 ?3.0 ?2.0 ?1.0 inl error (lsb) 0 1.0 4.0 3.0 2.0 16384 32768 49152 65536 2159 g01 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 2159 g02 output code 0 16384 32768 49152 65536 output code 32836 1000 0 3000 2000 count 4000 5000 10000 9000 8000 7000 6000 32842 32848 32854 32860 2159 g03
LTC2159 11 2159f typical p er f or m ance c harac t eris t ics snr vs input frequency, C1dbfs, 20msps, 2v range 2nd, 3rd harmonic vs input frequency, C1dbfs, 20msps, 2v range 2nd, 3rd harmonic vs input frequency, C1dbfs, 20msps, 1v range sfdr vs input level, f in = 70mhz, 20msps, 2v range i vdd vs sample rate, 5mhz, C1dbfs wine wave input i ovdd vs sample rate, 5mhz, C1dbfs sine wave input snr vs sense, f in = 5mhz, C1dbfs input frequency (mhz) 0 72 71 70 78 77 76 75 74 73 snr (dbfs) 50 100 150 200 250 300 2159 g04 single-ended encode differential encode 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 2159 g05 2nd 3rd 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 2159 g06 2nd 3rd input level (dbfs) ?80 60 50 40 30 20 80 70 sfdr (dbc and dbfs) 90 100 130 120 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 2159 g07 dbfs dbc sample rate (msps) 0 21 17 25 29 i vdd (ma) 4 8 12 16 20 2159 g08 cmos outputs 3.5ma lvds outputs sample rate (msps) 0 10 0 20 30 40 50 i ovdd (ma) 4 8 12 16 20 2159 g09 1.8v cmos 1.75ma lvds 3.5ma lvds 1.2v cmos sense pin (v) 0.6 71 70 72 73 78 77 76 75 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 2159 g10
LTC2159 12 2159f p in func t ions (pins that are the same for all digital output modes) v cm (pin 1): common mode bias output. nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs. bypass to ground with a 0.1f ceramic capacitor. a in + (pin 2): positive differential analog input. a in C (pin 3): negative differential analog input. gnd (pins 4, 10, 11, 14, 20, 43, exposed pad pin 49): adc power ground. the exposed pad must be soldered to the pcb ground. refh (pins 5, 7): adc high reference. see the applica- tions information section for recommended bypassing circuits for refh and refl. refl (pins 6, 8): adc low reference. see the applications information section for recommended bypassing circuits for refh and refl. par/ ser (pin 9): programming mode selection pin. con- nect to ground to enable the serial programming mode. cs , sck, sdi, sdo become a serial interface that control the a/d operating modes. connect to v dd to enable the parallel programming mode where cs , sck, sdi, sdo become parallel logic inputs that control a reduced set of the a/d operating modes. par/ ser should be connected directly to ground or v dd and not be driven by a logic signal. v dd (pins 12, 13, 47, 48): analog power supply, 1.7v to 1.9v. bypass to ground with 0.1f ceramic capacitors. adjacent pins can share a bypass capacitor. enc + (pin 15): encode input. conversion starts on the rising edge. enc C (pin 16): encode complement input. conversion starts on the falling edge. tie to gnd for single-ended encode mode. cs (pin 17): serial interface chip select input. in serial programming mode (par/ ser = 0v), cs is the serial in- terface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in the parallel programming mode (par/ ser = v dd ), cs controls the clock duty cycle stabilizer (see table 2). cs can be driven with 1.8v to 3.3v logic. sck (pin 18): serial interface clock input. in serial programming mode, (par/ ser = 0v), sck is the serial interface clock input. in the parallel programming mode (par/ ser = v dd ), sck controls the digital output mode (see table 2). sck can be driven with 1.8v to 3.3v logic. sdi (pin 19): serial interface data input. in serial program- ming mode, (par/ ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in the parallel program- ming mode (par/ ser = v dd ), sdi can be used together with sdo to power down the part (table 2). sdi can be driven with 1.8v to 3.3v logic. ognd (pin 31): output driver ground. must be shorted to the ground plane by a very low inductance path. use multiple vias close to the pin. ov dd (pin 32): output driver supply. bypass to ground with a 0.1f ceramic capacitor. sdo (pin 44): serial interface data output. in serial pro- gramming mode, (par/ ser = 0v), sdo is the optional serial interface data output. data on sdo is read back from the mode control registers and can be latched on the fall- ing edge of sck. sdo is an open-drain nmos output that requires an external 2k pull-up resistor to 1.8v C 3.3v. if read back from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. in the parallel programming mode (par/ ser = v dd ), sdo can be used together with sdi to power down the part (table 2). when used as an input, sdo can be driven with 1.8v to 3.3v logic through a 1k series resistor. v ref (pin 45): reference voltage output. bypass to ground with a 2.2f ceramic capacitor. the output voltage is nominally 1.25v. sense (pin 46): reference programming pin. connecting sense to v dd selects the internal reference and a 1v input range. connecting sense to ground selects the internal reference and a 0.5v input range. an external reference between 0.625v and 1.3v applied to sense selects an input range of 0.8 ? v sense .
LTC2159 13 2159f pin f unc t ions full rate cmos output mode all pins below have cmos output levels (ognd to o vdd ) d0 to d15 (pins 21-28, 33-40): digital outputs. d15 is the msb. clkout C (pin 29): inverted version of clkout + . clkout + (pin 30): data output clock. the digital outputs normally transition at the same time as the falling edge of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. dnc (pin 41): do not connect this pin. of (pin 42): overflow/underflow digital output. of is high when an overflow or underflow has occurred. double data rate cmos output mode all pins below have cmos output levels (ognd to o vdd ) d0_1 to d14_15 (pins 22, 24, 26, 28, 34, 36, 38, 40): double data rate digital outputs. two data bits are mul - tiplexed onto each output pin. the even data bits (d0, d2, d4, d6, d8, d10, d12, d14) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11, d13, d15) appear when clkout + is high. dnc (pins 21, 23, 25, 27, 33, 35, 37, 39, 41): do not connect these pins. clkout C (pin 29): inverted version of clkout + . clkout + (pin 30): data output clock. the digital outputs normally transition at the same time as the falling and ris- ing edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. of (pin 42): overflow/underflow digital output. of is high when an overflow or underflow has occurred. double data rate lvds output mode all pins below have lvds output levels. the output current level is programmable. there is an optional internal 100 termination resistor between the pins of each lvds output pair. d0_1 C /d0_1 + to d14_15 C /d14_15 + (pins 21/22, 23/24, 25/26, 27/28, 33/34, 35/36, 37/38, 39/40): double data rate digital outputs. two data bits are multiplexed onto each differential output pair. the even data bits (d0, d2, d4, d6, d8, d10, d12, d14) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11, d13, d15) appear when clkout + is high. clkout C /clkout + (pins 39/40): data output clock. the digital outputs normally transition at the same time as the falling and rising edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. of C /of + (pins 41/42): overflow/underflow digital output. of + is high when an overflow or underflow has occurred.
LTC2159 14 2159f func t ional b lock diagra m converter operation the LTC2159 is a low power, 16-bit, 20msps a/d converter that is powered by a single 1.8v supply. the analog inputs should be driven differentially. the encode input can be driven differentially or single-ended for lower power con- sumption. the digital outputs can be cmos, double data rate cmos (to halve the number of output lines), or double data rate lvds (to reduce digital noise in the system). many additional features can be chosen by programming the mode control registers through a serial spi port. figure 1. functional block diagram a pplica t ions i n f or m a t ion analog input the analog inputs are differential cmos sample-and-hold circuits (figure 2). the inputs should be driven differentially around a common mode voltage set by the v cm output pin, which is nominally v dd /2. for the 2v input range, the inputs should swing from v cm C 0.5v to v cm + 0.5v. there should be 180 phase difference between the inputs. diff ref amp ref buf 2.2f 0.1f 0.1f clock/duty cycle control range select 1.25v reference enc + refh refl enc ? sdo cs ognd of ovdd d15 clkout ? clkout + d0 2159 bd sense v ref 2.2f v cm 0.1f v dd /2 mode control registers output drivers sck par/ ser sdi ? ? ? refl internal clock signals refh s/h analog input 16-bit adc core correction logic v dd gnd
LTC2159 15 2159f a pplica t ions i n f or m a t ion figure 2. equivalent input circuit transformer coupled circuits figure 3 shows the analog input being driven by an rf transformer with a center-tapped secondary. the center tap is biased with v cm , setting the a/d input at its optimal dc level. at higher input frequencies a transmission line balun transformer (figures 4 through 6) has better bal- ance, resulting in lower a/d distortion. amplifier circuits figure 7 shows the analog input being driven by a high speed differential amplifier. the output of the amplifier is ac coupled to the a/d so the amplifiers output common mode voltage can be optimally set to minimize distortion. at very high frequencies an rf gain block will often have lower distortion than a differential amplifier. if the gain block is single-ended, then a transformer circuit (figures 4 through 6) should convert the signal to differential before driving the a/d. figure 3. analog input circuit using a transformer. recommended for input frequencies from 5mhz to 70mhz c sample 5pf r on 15 r on 15 v dd v dd LTC2159 a in + 2159 f02 c sample 5pf v dd a in ? enc ? enc + 1.2v 10k 1.2v 10k c parasitic 1.8pf c parasitic 1.8pf 10 10 25 25 25 25 50 a in + a in ? 12pf 0.1f v cm LTC2159 analog input 0.1f t1 1:1 t1: ma/com mabaes0060 resistors, capacitors are 0402 package size 2159 f03 0.1f single-ended input for applications less sensitive to harmonic distortion, the a in + input can be driven single-ended with a 1v p-p signal centered around v cm . the a in C input should be connected to v cm and the v cm bypass capacitor should be increased to 2.2f. with a single-ended input the harmonic distortion and inl will degrade, but the noise and dnl will remain unchanged. input drive circuits input filtering if possible, there should be an rc lowpass filter right at the analog inputs. this lowpass filter isolates the drive circuitry from the a/d sample-and-hold switching, and also limits wideband noise from the drive circuitry. figure 3 shows an example of an input rc filter. the rc component values should be chosen based on the applications input frequency.
LTC2159 16 2159f applica t ions in f or m a t ion figure 4. recommended front end circuit for input frequencies from 5mhz to 150mhz figure 5. recommended front end circuit for input frequencies from 150mhz to 250mhz figure 6. recommended front end circuit for input frequencies above 250mhz figure 7. front end circuit using a high speed differential amplifier 25 25 50 12 12 0.1f a in + a in ? 8.2pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1tl resistors, capacitors are 0402 package size 2159 f04 LTC2159 25 25 50 0.1f a in + a in ? 1.8pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1tl resistors, capacitors are 0402 package size 2159 f05 LTC2159 25 25 50 0.1f 4.7nh 4.7nh a in + a in ? 0.1f v cm analog input t1: ma/com etc1-1-13 resistors, capacitors are 0402 package size 2159 f06 LTC2159 t1 0.1f 0.1f 25 25 200 200 0.1f a in + a in ? 12pf 0.1f v cm LTC2159 2159 f07 ? + analog input high speed differential amplifier 0.1f 12pf
LTC2159 17 2159f a pplica t ions i n f or m a t ion figure 8a. reference circuit v ref refh refh sense c1 tie to v dd for 2v range; tie to gnd for 1v range; range = 1.6 ? v sense for 0.625v < v sense < 1.300v 1.25v refl refl internal adc high reference buffer 2159 f08 ltc2 159 5 0.8x diff amp internal adc low reference c1: 2.2f low inductance interdigitated capacitor tdk clle1ax7s0g225m murata lla219c70g225m avx w2l14z225m or equivalent 1.25v bandgap reference 0.625v range detect and control 2.2f c2 0.1f c3 0.1f + + ? ? ? ? + + reference the LTC2159 has an internal 1.25v voltage reference. for a 2v input range using the internal reference, connect sense to v dd . for a 1v input range using the internal reference, connect sense to ground. for a 2v input range with an external reference, apply a 1.25v reference voltage to sense (figure 9). the input range can be adjusted by applying a voltage to sense that is between 0.625v and 1.30v. the input range will then be 1.6 ? v sense . the v ref , refh and refl pins should be bypassed as shown in figure 8a. a low inductance 2.2f interdigitated capacitor is recommended for the bypass between refh and refl. this type of capacitor is available at a low cost from multiple suppliers. alternatively, c1 can be replaced by a standard 2.2f capacitor between refh and refl. the capacitor should be as close to the pins as possible (not on the back side of the circuit board). figure 8b. alternative refh/refl bypass circuit figure 8c. recommended layout for the refh/refl bypass circuit in figure 8a figure 8d. recommended layout for the refh/refl bypass circuit in figure 8b refh refh refl refl 2159 f08b ltc2 159 capacitors are 0402 package size c3 0.1f c1 2.2f c2 0.1f figures 8c and 8d show the recommended circuit board layout for the refh/refl bypass capacitors. note that in figure 8c, every pin of the interdigitated capacitor (c1) is connected since the pins are not internally connected in some vendors capacitors. in figure 8d, the refh and refl pins are connected by short jumpers in an internal layer. to minimize the inductance of these jumpers they can be placed in a small hole in the gnd plane on the second board layer. figure 9. using an external 1.25v reference sense 1.25v external reference 2.2f 1f v ref 2159 f09 LTC2159
LTC2159 18 2159f encode input the signal quality of the encode inputs strongly affects the a/d noise performance. the encode inputs should be treated as analog signalsdo not route them next to digital traces on the circuit board. there are two modes of operation for the encode inputs: the differential encode mode (figure 10), and the single-ended encode mode (figure 11). applica t ions in f or m a t ion figure 12. sinusoidal encode drive figure 13. pecl or lvds encode drive encode input. enc + can be taken above v dd (up to 3.6v) enabling 1.8v to 3.3v cmos logic levels to be used. the enc + threshold is 0.9v. for good jitter performance enc + should have fast rise and fall times. if the encode signal is turned off or drops below approxi- mately 500khz, the a/d enters nap mode. clock duty cycle stabilizer for good performance the encode signal should have a 50% (10%) duty cycle. if the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 10% to 90% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the encode signal changes frequency, the duty cycle stabilizer circuit requires one hundred clock cycles to lock onto the input clock. the duty cycle stabilizer is enabled by mode control register a2 (serial programming mode), or by cs (parallel programming mode). for applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. if the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (10%) duty cycle. the duty cycle stabilizer should not be used below 5msps. figure 10. equivalent encode input circuit for differential encode mode figure 11. equivalent encode input circuit for single-ended encode mode. the differential encode mode is recommended for sinu- soidal, pecl, or lvds encode inputs (figures 12, 13). the encode inputs are internally biased to 1.2v through 10k? equivalent resistance. the encode inputs can be taken above v dd (up to 3.6v), and the common mode range is from 1.1v to 1.6v. in the differential encode mode, enc C should stay at least 200mv above ground to avoid falsely triggering the single-ended encode mode. for good jitter performance enc + and enc C should have fast rise and fall times. the single ended encode mode should be used with cmos encode inputs. to select this mode, enc C is con- nected to ground and enc + is driven with a square wave v dd LTC2159 2159 f10 enc ? enc + 15k v dd differential comparator 30k 30k enc + enc ? 2159 f11 0v 1.8v to 3.3v LTC2159 cmos logic buffer 50 100 0.1f 0.1f 0.1f t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 LTC2159 2159 f12 enc ? enc + t1 enc + enc ? pecl or lvds clock 0.1f 0.1f 2159 f13 LTC2159
LTC2159 19 2159f a pplica t ions i n f or m a t ion digital outputs digital output modes the LTC2159 can operate in three digital output modes: full rate cmos, double data rate cmos (to halve the number of output lines), or double data rate lvds (to reduce digital noise in the system.) the output mode is set by mode control register a3 (serial programming mode), or by sck (parallel programming mode). note that double data rate cmos cannot be selected in the parallel programming mode. full rate cmos mode in full rate cmos mode the data outputs (d0 to d15), overflow (of), and the data output clocks (clkout + , clkout C ) have cmos output levels. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. ov dd can range from 1.1v to 1.9v, allowing 1.2v through 1.8v cmos logic outputs. for good performance, the digital outputs should drive minimal capacitive loads. if the load capacitance is larger than 10pf, a digital buffer should be used. double data rate cmos mode in double data rate cmos mode, two data bits are mul- tiplexed and output on each data pin. this reduces the number of digital lines by eight, simplifying board routing and reducing the number of input pins needed to receive the data. the data outputs (d0_1, d2_3, d4_5, d6_7, d8_9, d10_11, d12_13, d14_15), overflow (of), and the data output clocks (clkout + , clkout C ) have cmos output levels. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. ov dd can range from 1.1v to 1.9v, allowing 1.2v through 1.8v cmos logic outputs. for good performance, the digital outputs should drive minimal capacitive loads. if the load capacitance is larger than 10pf, a digital buffer should be used. double data rate lvds mode in double data rate lvds mode, two data bits are multi - plexed and output on each differential output pair. there are eight lvds output pairs (d0_1 + /d0_1 C through d14_15 + / d14_15 C ) for the digital output data. overflow (of + /of C ) and the data output clock (clkout + /clkout C ) each have an lvds output pair. by default the outputs are standard lvds levels: 3.5ma output current and a 1.25v output common mode volt - age. an external 100? differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. in lvds mode, ov dd must be 1.8v. programmable lvds output current in lvds mode, the default output driver current is 3.5ma. this current can be adjusted by serially programming mode control register a3. available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4ma and 4.5ma. optional lvds driver internal termination in most cases using just an external 100? termination resistor will give excellent lvds signal integrity. in addi - tion, an optional internal 100? termination resistor can be enabled by serially programming mode control register a3. the internal termination helps absorb any reflections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. overflow bit the overflow output bit outputs a logic high when the analog input is either overranged or underranged. the overflow bit has the same pipeline latency as the data bits.
LTC2159 20 2159f phase-shifting the output clock in full rate cmos mode the data output bits normally change at the same time as the falling edge of clkout + , so the rising edge of clkout + can be used to latch the output data. in double data rate cmos and lvds modes the data output bits normally change at the same time as the falling and rising edges of clkout + . to allow adequate setup and hold time when latching the data, the clkout + signal may need to be phase-shifted relative to the data output bits. most fpgas have this feature; this is generally the best place to adjust the timing. figure 14. phase-shifting clkout the LTC2159 can also phase-shift the clkout + /clkout C signals by serially programming mode control register a2. the output clock can be shifted by 0, 45, 90, or 135. to use the phase-shifting feature the clock duty cycle stabilizer must be turned on. another control register bit can invert the polarity of clkout + and clkout C , independently of the phase-shift. the combination of these two features enables phase-shifts of 45 up to 315 (figure 14). applica t ions in f or m a t ion table 1. output codes vs input voltage a in + C a in C (2v range) of d15 C d0 (offset binary) d15 C d0 (2s complement) >1.000000v +0.999970v +0.999939v 1 0 0 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 1111 0111 1111 1111 1111 0111 1111 1111 1110 +0.000030v +0.000000v C0.000030v C0.000061v 0 0 0 0 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1111 1110 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 C0.999939v C1.000000v < C1.000000v 0 0 1 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0001 1000 0000 0000 0000 1000 0000 0000 0000 clkout + d0-d15, of phase shift 0 45 90 135 180 225 270 315 clkinv 0 0 0 0 1 1 1 1 clkphase1 mode control bits 0 0 1 1 0 0 1 1 clkphase0 0 1 0 1 0 1 0 1 2159 f14 enc +
LTC2159 21 2159f a pplica t ions i n f or m a t ion data format table 1 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. by default the output data format is offset binary. the 2s complement format can be selected by serially program- ming mode control register a4. digital output randomizer interference from the a/d digital outputs is sometimes unavoidable. digital interference may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can cause unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. the digital output is randomized by applying an exclusive- or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied an exclusive-or operation is applied between the lsb and all other bits. the lsb, of and clkout outputs are not affected. the output randomizer is enabled by serially programming mode control register a4. figure 15. functional equivalent of digital output randomizer figure 16. unrandomizing a randomized digital output signal alternate bit polarity another feature that reduces digital feedback on the circuit board is the alternate bit polarity mode. when this mode is enabled, all of the odd bits (d1, d3, d5, d7, d9, d11, d13, d15) are inverted before the output buffers. the even bits (d0, d2, d4, d6, d8, d10, d12, d14), of and clkout are not affected. this can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for very small analog input signals. when there is a very small signal at the input of the a/d that is centered around mid-scale, the digital outputs toggle between mostly 1s and mostly 0s. this simultaneous switching of most of the bits will cause large currents in the ground plane. by inverting every other bit, the alternate bit polarity mode makes half of the bits transition high while half of the bits transition low. this cancels current flow in the ground plane, reducing the digital noise. the digital output is decoded at the receiver by inverting the odd bits (d1, d3, d5, d7, d9, d11, d13, d15.) the alternate bit polarity mode is independent of the digital output randomizereither, both or neither function can be on at the same time. the alternate bit polarity mode is enabled by serially programming mode control register a4. clkout clkout of d15/d0 d14/d0 ? ? ? d2/d0 d1/d0 d0 2159 f15 of d15 d14 d2 d1 d0 randomizer on d15 fpga pc board d14 ? ? ? d2 d1 d0 2159 f16 d0 d1/d0 d2/d0 d14/d0 d15/d0 of clkout LTC2159
LTC2159 22 2159f digital output test patterns to allow in-circuit testing of the digital interface to the a/d, there are several test modes that force the a/d data outputs (of, d15 to d0) to known values: all 1s: all outputs are 1 all 0s: all outputs are 0 alternating: outputs change from all 1s to all 0s on alternating samples. checkerboard: outputs change from 10101010101010101 to 01010101010101010 on alternating samples. the digital output test patterns are enabled by serially programming mode control register a4. when enabled, the test patterns override all other formatting modes: 2s complement, randomizer, alternate bit polarity. output disable the digital outputs may be disabled by serially program - ming mode control register a3. all digital outputs includ- ing of and clkout are disabled. the high-impedance disabled state is intended for in-circuit testing or long periods of inactivityit is too slow to multiplex a data bus between multiple converters at full speed. when the outputs are disabled the adc should be put into either sleep or nap mode. sleep and nap modes the a/d may be placed in sleep or nap modes to conserve power. in sleep mode the entire device is powered down, resulting in 1mw power consumption. the amount of time required to recover from sleep mode depends on the size of the bypass capacitors on v ref , refh, and refl. for the suggested values in figure 8, the a/d will stabilize after 2ms. applica t ions in f or m a t ion in nap mode the a/d core is powered down while the internal reference circuits stay active, allowing faster wake-up than from sleep mode. recovering from nap mode requires at least 100 clock cycles. if the application demands very accurate dc settling then an additional 50s should be allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current as the a/d leaves nap mode. sleep mode and nap mode are enabled by mode control register a1 (serial programming mode), or by sdi and sdo (parallel programming mode). device programming modes the operating modes of the LTC2159 can be programmed by either a parallel interface or a simple serial interface. the serial interface has more flexibility and can program all available modes. the parallel interface is more limited and can only program some of the more commonly used modes. parallel programming mode to use the parallel programming mode, par/ ser should be tied to v dd . the cs , sck, sdi and sdo pins are binary logic inputs that set certain operating modes. these pins can be tied to v dd or ground, or driven by 1.8v, 2.5v, or 3.3v cmos logic. when used as an input, sdo should be driven through a 1k? series resistor. table 2 shows the modes set by cs, sck, sdi and sdo. table 2. parallel programming mode control bits (par/ ser = v dd ) pin description cs clock duty cycle stabilizer control bit 0 = clock duty cycle stabilizer off 1 = clock duty cycle stabilizer on sck digital output mode control bit 0 = full rate cmos output mode 1 = double data rate lvds output mode (3.5ma lvds current, internal t ermination off) sdi/sdo power-down control bits 00 = normal operation 01 = not used 10 = nap mode 11 = sleep mode (entire device powered down)
LTC2159 23 2159f serial programming mode to use the serial programming mode, par/ ser should be tied to ground. the cs, sck, sdi and sdo pins become a serial interface that program the a/d mode control registers. data is written to a register with a 16-bit serial word. data can also be read back from a register to verify its contents. serial data transfer starts when cs is taken low. the data on the sdi pin is latched at the first 16 rising edges of sck. any sck rising edges after the first 16 are ignored. the data transfer ends when cs is taken high again. the first bit of the 16-bit input word is the r/w bit. the next seven bits are the address of the register (a6:a0). the final eight bits are the register data (d7:d0). if the r/w bit is low, the serial data (d7:d0) will be writ- ten to the register set by the address bits (a6:a0). if the r/w bit is high, data in the register set by the address bits (a6:a0) will be read back on the sdo pin (see the timing diagrams). during a read back command the register is not updated and data on sdi is ignored. the sdo pin is an open drain output that pulls to ground with a 200? impedance. if register data is read back through sdo, an external 2k pull-up resistor is required. if serial data is only written and read back is not needed, then sdo can be left floating and no pull-up resistor is needed. table 3 shows a map of the mode control registers. software reset if serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. the first serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset, bit d7 in the reset register is written with a logic 1. after the reset spi write command is complete, bit d7 is automatically set back to zero. a pplica t ions i n f or m a t ion table 3. serial programming mode register map (par/ ser = gnd) register a0: reset register (address 00h) d7 d6 d5 d4 d3 d2 d1 d0 reset x x x x x x x bits 7 reset software reset bit 0 = not used 1 = software reset. all mode control registers are reset to 00h. the adc is momentarily placed in sleep mode. this bit is automatically set back to zero at the end of the spi write command. the reset register is write-only . data read back from the reset register will be random. bits 6-0 unused, dont care bits register a1: power down register (address 01h) d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x pwroff1 pwroff0 bits 7-2 unused, dont care bits bits 1-0 pwroff1: pwroff0 power down control bits 00 = normal operation 01 = not used 10 = nap mode 11 = sleep mode
LTC2159 24 2159f applica t ions in f or m a t ion register a2: timing register (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 x x x x clkinv clkphase1 clkphase0 dcs bits 7-4 unused, dont care bits bit 3 clkinv output clock invert bit 0 = normal clkout polarity (as shown in the timing diagrams) 1 = inverted clkout polarity bits 2-1 clkphase1: clkphase0 output clock phase delay bits 00 = no clkout delay (as shown in the timing diagrams) 01 = clkout + /clkout C delayed by 45 (clock period 1/8) 10 = clkout + /clkout C delayed by 90 (clock period 1/4) 11 = clkout + /clkout C delayed by 135 (clock period 3/8) note: if the clkout phase delay feature is used, the clock duty cycle stabilizer must also be turned on. bit 0 dcs clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer off 1 = clock duty cycle stabilizer on register a3: output mode register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 x ilvds2 ilvds1 ilvds0 termon outoff outmode1 outmode0 bit 7 unused, dont care bit bits 6-4 ilvds2: ilvds0 lvds output current bits 000 = 3.5ma l vds output driver current 001 = 4.0ma lvds output driver current 010 = 4.5ma lvds output driver current 011 = not used 100 = 3.0ma lvds output driver current 101 = 2.5ma lvds output driver current 110 = 2.1ma lvds output driver current 111 = 1.75ma lvds output driver current bit 3 termon lvds internal t ermination bit 0 = internal termination off 1 = internal termination on. lvds output driver current is 2x the current set by ilvds2:ilvds0.
LTC2159 25 2159f bit 2 outoff output disable bit 0 = digital outputs are enabled. 1 = digital outputs are disabled and have high output impedance. note: if the digital outputs are disabled the part should also be put in sleep mode or nap mode. bits 1-0 outmode1: outmode0 digital output mode control bits 00 = full rate cmos output mode 01 = double data rate lvds output mode 10 = double data rate cmos output mode 11 = not used register a4: da ta format register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 x x outtest2 outtest1 outtest0 abp rand twoscomp bits 7-6 unused, dont care bits bits 5-3 outtest2: outtest0 digital output test pattern bits 000 = digital output t est patterns off 001 = all digital outputs = 0 011 = all digital outputs = 1 101 = checkerboard output pattern. of, d15-d0 alternate between 1 0101 0101 0101 0101 and 0 1010 1010 1010 1010. 111 = alternating output pattern. of, d15-d0 alternate between 0 0000 0000 0000 0000 and 1 1111 1111 1111 1111. note: other bit combinations are not used. bit 2 abp alternate bit polarity mode control bit 0 = alternate bit polarity mode off 1 = alternate bit polarity mode on. forces the output format to be offset binar y. bit 1 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bits 0 twoscomp two s complement mode control bit 0 = offset binary data format 1 = twos complement data format a pplica t ions i n f or m a t ion
LTC2159 26 2159f grounding and bypassing the LTC2159 requires a printed circuit board with a clean unbroken ground plane in the first layer beneath the adc. a multilayer board with an internal ground plane is rec - ommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , v ref , refh and refl pins. bypass capacitors must be located as close to the pins as pos- sible. size 0402 ceramic capacitors are recommended. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. applica t ions in f or m a t ion of particular importance is the capacitor between refh and refl. this capacitor should be on the same side of the circuit board as the a/d, and as close to the device as possible. the analog inputs, encode signals, and digital outputs should not be routed next to each other. ground fill and grounded vias should be used as barriers to isolate these signals from each other. heat transfer most of the heat generated by the LTC2159 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. this pad should be connected to the internal ground planes by an array of vias.
LTC2159 27 2159f typical a pplica t ions silkscreen top top side
LTC2159 28 2159f typical applica t ions inner layer 2 inner layer 3
LTC2159 29 2159f typical applica t ions inner layer 4 bottom side inner layer 5
LTC2159 30 2159f typical applica t ions v cm a in + a in ? gnd refh refl refh refl par/ ser gnd gnd v dd a in + a in ? d11 d10 d9 d8 ov dd ognd clkout + clkout ? d7 d6 d5 d4 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 spi port 2159 ta02 gnd enc + enc ? cs sck sdi v dd v dd d0 d1 d2 d3 24232221 191817161514 3738394041424344 4647 45 48 13 v dd v dd v dd sense v ref sdo sdo gnd of d15dnc d14 d13 d12 0v dd c37 0.1f LTC2159 c15 0.1f c21 0.1f c18 0.1f gnd 20 sense digital outputs c32 0.1f r51 100 encode clock c28 0.1f c19 0.1f c23 2.2f c51 0.1f + ? + ? ? + ? + cn1 par/ ser
LTC2159 31 2159f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion uk package 48-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1704 rev c) 7.00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (wkkd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 chamfer c = 0.35 0.40 0.10 4847 1 2 bottom view?exposed pad 5.50 ref (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uk48) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 5.50 ref (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc package outline 5.15 0.10 5.15 0.10 5.15 0.05 5.15 0.05 r = 0.10 typ
LTC2159 32 2159f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0312 ? printed in usa typical a pplica t ion r ela t e d p ar t s part number description comments adcs ltc2259-14/ltc2260-14/ ltc2261-14 14-bit, 80msps/105msps/125msps 1.8v adcs, ultralow power 89mw/106mw/127mw, 73.4db snr, 85db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm 6mm qfn-40 ltc2262-14 14-bit, 150msps 1.8v adc, ultralow power 149mw, 72.8db snr, 88db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm 6mm qfn-40 ltc2266-14/ltc2267-14/ ltc2268-14 14-bit, 80msps/105msps/125msps 1.8v dual adcs, ultralow power 216mw/250mw/293mw, 73.4db snr, 85db sfdr, serial lvds outputs, 6mm 6mm qfn-40 ltc2266-12/ltc2267-12/ ltc2268-12 12-bit, 80msps/105msps/125msps 1.8v dual adcs, ultralow power 216mw/250mw/293mw, 70.5db snr, 85db sfdr, serial lvds outputs, 6mm 6mm qfn-40 ltc2208 16-bit, 130msps 3.3v adc 1250mw, 77.7db snr, 100db sfdr, cmos/lvds outputs, 9mm 9mm qfn-64 ltc2207/ltc2206 16-bit, 105msps/80msps 3.3v adcs 900mw/725mw, 77.9db snr, 100db sfdr, cmos outputs, 7mm 7mm qfn-48 ltc2217/ltc2216 16-bit, 105msps/80msps 3.3v adcs 1190mw/970mw, 81.2db snr, 100db sfdr, cmos/lvds outputs, 9mm 9mm qfn-64 rf mixers/demodulators ltc5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator ltc5527 400mhz to 3.7ghz high linearity downconverting mixer 24.5dbm iip3 at 900mhz, 23.5dbm iip3 at 3.5ghz, nf = 12.5db, 50 single-ended rf and lo ports ltc5557 400mhz to 3.8ghz high linearity downconverting mixer 23.7dbm iip3 at 2.6ghz, 23.5dbm iip3 at 3.5ghz, nf = 13.2db, 3.3v supply operation, integrated transformer ltc5575 800mhz to 2.7ghz direct conversion quadrature demodulator high iip3: 28dbm at 900mhz, integrated lo quadrature generator, integrated rf and lo transformer amplifiers/filters ltc6412 800mhz, 31db range, analog-controlled variable gain amplifier continuously adjustable gain control, 35dbm oip3 at 240mhz, 10db noise figure, 4mm 4mm qfn-24 ltc6420-20 1.8ghz dual low noise, low distortion differential adc drivers for 300mhz if fixed gain 10v/v, 1nv/ hz total input noise, 80ma supply current per amplifier, 3mm 4mm qfn-20 ltc6421-20 1.3ghz dual low noise, low distortion differential adc drivers fixed gain 10v/v, 1nv/ hz total input noise, 40ma supply current per amplifier, 3mm 4mm qfn-20 ltc6605-7/ltc6605-10/ ltc6605-14 dual matched 7mhz/10mhz/14mhz filters with adc drivers dual matched 2nd order lowpass filters with differential drivers, pin-programmable gain, 6mm 3mm dfn-22 signal chain receivers lt m ? 9002 14-bit dual channel if/baseband receiver subsystem integrated high speed adc, passive filters and fixed gain differential amplifiers integral non-linearity (inl) s/h output drivers 16-bit adc core clock control d15 ? ? ? d0 20mhz clock analog input 2159 ta03a cmos, ddr cmos or ddr lvds outputs 1.8v v dd 1.8v ov dd gnd ognd output code 0 ?4.0 ?3.0 ?2.0 ?1.0 inl error (lsb) 0 1.0 4.0 3.0 2.0 16384 32768 49152 65536 2159 ta03b

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